The present invention refers to a voltage boosting device, and in particular for increasing the speed of power-up of multilevel nonvolatile memories.
As is known, in order to correctly read multilevel nonvolatile memories, it is necessary to supply the memory cells to be read with high voltages, i.e., higher than the supply voltages normally available. For this purpose, voltage boosting devices are employed that use voltage boosters (charge pumps) that are able to raise the voltage above the supply voltage, together with regulator stages for stabilizing the read voltage at around the nominal values required.
According to a very widespread design, a first charge pump, with low consumption and low performance, is kept in continuous operation, also in standby conditions, whereas a second charge pump, with high performance, intervenes only when the memory is in the active state. In practice, the low consumption pump has the purpose of compensating the discharging of the high voltage nodes that is due to inevitable leakage currents during the standby state. Since these leakage currents are normally somewhat contained, the low consumption pump, albeit having a low level of performance, is sufficient for the purpose.
Since the read voltage at input of the memory in the active state is already at the desired value and it is not necessary to raise it any further, reading upon re-entry from the standby condition is rendered faster, and the memory is, as a whole, faster. In addition, since the pump used in standby absorbs a very low power, consumption of the memory is not significantly increased.
Known devices, however, present a number of drawbacks. In fact, if at power-up it is not immediately necessary to carry out operations of memory programming or reading, the memory itself is set in standby. In this case, the high performance pump is deactivated, and the read voltage must be brought to the nominal value by means of the low consumption pump, which, however, is not able to supply high charge currents. Consequently, the time required for the memory to reach nominal operating conditions, such as to guarantee proper execution of the programming and, in particular, reading, is long.
On the other hand, even when reading is requested immediately at power-up and the memory is set in the active state, the memory is not able to carry out the operations requested. In order to prevent errors, in fact, the read voltage must stabilize at around the nominal value; consequently, it is necessary to wait for a clock cycle for the generation of a sync signal (normally called ATD) which enables reading. Thus, the time required for accessing the content of the memory following the power-up phase is long and represents a limitation of the performance of the memory itself.
The disclosed embodiment of the present invention provides a device for raising the voltage which, in a nonvolatile memory, allows a read voltage to rapidly reach a nominal value, in particular where at power-up the memory is set in standby.
A voltage boosting device is provided, the device including a voltage regulator and a charge pump having an output terminal supplying a read voltage at a nominal value, the voltage regulator having a regulation terminal connected to the output terminal and a control output supplying a control voltage that has a first control level when the read voltage is lower than a preset value; the recharge pump having an enable terminal and an output connected to the output terminal; and an enable circuit having a first input connected to the control output, a second input receiving a power-up signal, and a pump enable output connected to the enable terminal of the charge pump and supplying a pump enable signal, the pump enable signal being set at a first logic level for activating the charge pump at least upon receiving the power-up signal.
In accordance with another aspect of the invention, the enable circuit includes a memory circuit having an input connected to the second input of the enable circuit and an output supplying a power-up memory signal switching to a first level upon receiving the power-up signal; and an activation circuit having inputs connected to the control output and to the first node, and an activation mode connected to the pump enable terminal for supplying the pump enable signal in the presence of the first level of a bistable reset signal and as long as the control voltage has the first control value.
In accordance with another aspect of the invention, the enable circuit includes a memory circuit having an input connected to the second input of the enable circuit, and an output supplying a power-up memory signal switching to a first level upon receiving the power-up signal and also including a sync stage having a first input, a second input, and a sink output, the first input and the second input of the sink stage connected, respectively, to the output of the memory circuit and to a chip enable terminal supplying a chip enable signal, and the sync output supplying a power-up sync signal having a pulse when the read voltage reaches the nominal value and the chip enable signal is set at an active value.